TC2050-IDC · 10-pin Debug Cable with Legs, No Connector

Short description

Ten-pin debug and programming cable with spring pins that lands straight on the board — no connector on the target, just ten contact pads and six holes. The four legs hold it there while you work. At the other end, a standard 2.54 mm (0.1″) ribbon header that fits nearly every debugger.

Connections

Pin assignment: contact n is on connector pin n — the cable is wired straight through.

Compatible: programmers with a 10-pin 2.54 mm pin header — among them PEmicro Multilink and Cyclone, and the Intel/Altera USB-Blaster.

Not, or not directly, compatible

• 10-pin, 2 × 5, 1.27 mm (0.05″) — Cortex connector, e.g. Keil ULINK2: TC2050-IDC-050-ALL
• 20-pin, 2 × 10, 2.54 mm (0.1″) — ARM connector, e.g. SEGGER J-Link, Keil ULINK, ST-LINK/V2: through the adapter board COLL-ARM20-10-IDC, TC2050-ARM2010
• 12-pin — Lattice HW-USBN-2B: through the adapter board TC-LATTICE-10
• 14-pin, 2 × 7, 2 mm — Xilinx Platform Cable II: through the adapter board TC2050-XILINX
• 14-pin, 2 × 7, 2.54 mm (0.1″) — Renesas E1 / E2 / E8a / E20: through the adapter board TC-RENESAS
• 14-pin, 2 × 7, 2.54 mm (0.1″) — TI MSP-FET430: TC2050-IDC-430

New to the ten-pin family? Then the kit

If you are starting out with the ten-pin Tag-Connect family, have a look at our reduced-price TC2050 Evaluation Kit: cable, adapter board to the 20-pin ARM header, clip and grip to compare, a protective cap and a demo board with all footprints. It contains the cable without legs, because the clip only fits that footprint.

What this cable is for

The workbench. You place it, it latches, both hands are free — flash, debug, probe, with nobody holding a connector. That is what separates it from the no-legs version, which is made for the short grip in production.

What the legs do, and what they cost

The four legs are sprung latches. They snap into four holes of 2.375 mm and pull the spring pins onto the contact pads. Two fingers release them — and from that follows the one constraint the datasheet notes twice: there must be room for two fingers left and right of the footprint. On densely populated boards that rules it out more often than the holes do. Then take the TC2050-IDC-NL.

What to put on your board

• 10 contact pads, Ø 0.787 mm, 1.27 mm pitch, two rows 2.54 mm apart
• 2 holes Ø 0.991 mm for the alignment pins, 4 holes Ø 2.375 mm for the legs
• No tracks and no vias in the keep-out area between the pads
• No solder paste on the pads — a single opening in the paste mask ruins them
• No other signal closer than 0.5 mm to a contact pad

Two things you may do: the latch and alignment holes may be plated and used as vias. And the footprint belongs in your BOM as "Do Not Load" — the manufacturer prescribes the code DNL, or your assembler will try to buy a part that does not exist.

When ten contacts instead of six? SWD or Microchip's ICSP get by with six — for that there is the smaller TC2030-IDC. As soon as real JTAG comes into play, six no longer do: TCK, TMS, TDI and TDO need four lines instead of two, plus target voltage, ground and usually reset.

The ten-pin footprint is not tied to JTAG, though: for SWD there is a customary assignment on it as well — the same order with SWDIO instead of TMS and SWCLK instead of TCK, plus SWO on pin 6. One footprint, two modes — that is the real reason to provide for it at the first layout, if the debugger might change later.

The numbering — and why it does not look like the header

The signal number is the same at both ends: pad 7 on the board is pin 7 on the header. What differs is the position of the numbers. On the ten-pin footprint the count runs around: bottom row left to right, then back along the top. On the IDC header it alternates row by row instead.

If you know the six-pin TC2030, you will get this wrong: there the positions match the header (1 opposite 2, 3 opposite 4); from ten contacts on they do not. So lay the footprint out afresh instead of extending it — and take the alignment pin as the reference for orientation, not the row of contacts. Where the break comes from is explained under Connector numbering.

Typical assignment — JTAG and SWD

The cable connects straight through; which signal sits on which pin is decided by your debugger. In practice the reference is the assignment that our adapter board COLL-ARM20-10-IDC maps onto the 20-pin ARM header — it has become the customary one:

* Pin 5 is either ground or carries power from the debugger — selectable by a jumper on the COLL-ARM20-10-IDC (VCC / open / GND). Ground improves signal integrity; some debuggers supply 3.3 V rather than 5 V. ** nTRST on pin 9 is optional and likewise selected by a jumper on the adapter.

From prototype to series — one and the same footprint

The contact pads are designed for spring pins. The same technique works in the test fixtures of series production. The footprint you provide today for the debug cable can therefore be reused in the fixture — the debug interface does not have to be designed a second time, and it travels unchanged from development through pilot run into production test.

The service interface nobody sees

Because there is no connector on the board, there is none to see from the outside either. Many devices therefore carry the contact pads as a service interface: the technician has the cable in the case and installs new firmware on site — while the owner of the device is not handed the idea of plugging something in. Add the practical side: no connector that collects dirt, corrodes or wears out mechanically in the field, and no opening in the housing that would have to be designed for it.

A standard, not a one-off

The footprint is published and available in the common layout tools, and for the widespread programmers the matching cable comes off the shelf. For you that means: if another cable is needed, it is ordered — with an article number, from German stock, in two years as much as today. Nobody solders together a one-off whose pinout no one remembers after the next change of staff, and which exists exactly once.

Technical data

• Connectors: Plug-of-Nails™ spring pins to 2.54 mm (0.1″) ribbon
• Version: with legs ("legged")
• Cable length: approx. 200 mm (8″)
• Spring pins: rated for over 100,000 operations (manufacturer)
• On the board: no height, no mating connector

In use with these devices

ST-LINK/V2 and STLINK-V3SET (ST STM32) · SEGGER J-Link (ARM Cortex) · Keil (ARM) ULINK · PEmicro Multilink and Cyclone · Intel/Altera Byte Blaster and USB-Blaster · Xilinx Platform Cable · TI XDS100v2 · Digilent JTAG-HS2/HS3 · Lattice and various Renesas debuggers.

What counts is the connector, not the device name: compare the connector on your device with the table above. If it carries a different one, the route goes through an adapter board.

Debuggers with the classic 20-pin ARM header — J-Link, Keil ULINK and many older tools — connect through our adapter board COLL-ARM20-10-IDC. For debuggers with a finer header there are TC2050-IDC-050-ALL (1.27 mm) and TC2050-IDC-NL-050-STDC14 (ST-LINK V3).

Variants

TC2050-IDC-NL — no legs, smaller footprint. TC2050-IDC-430 — for TI MSP-FET430. TC2030-IDC — six pins, if SWD is enough.

Included

The cable only. Debugger and clip are not included.