Pin assignments of the Tag-Connect footprints

Behind the cables and adapters in the range there are only a few pin assignments. If you place a Tag-Connect footprint in your own layout, these are the tables you need: which signal sits on which contact, which contacts are mandatory and which are optional.

One page per interface:

• SWD — SWD pin assignment of the Tag-Connect footprints
• JTAG — JTAG pin assignment for microcontrollers and FPGAs
• UART — UART pin assignment of the Tag-Connect footprints
• ST-LINK (STDC14) — ST-LINK V3: STDC14 pin assignment with virtual COM port
• Other assignments — Other assignments: Microchip ICSP, MSP430, Cortex-20 with trace

Key points first. On 10 pins, the four JTAG signals sit on the same contacts for ARM, Xilinx and Lattice. On 6 pins, UART and 4-wire JTAG share the contacts. Cables without an adapter (TC2030-IDC, TC2050-IDC, TC2070-IDC) are wired 1:1 — the assignment is then determined by the connector on the debugger.

The position of the contacts is shown in Connector numbering.

All tables are derived from the pin assignments of the individual cables and adapters — manufacturer information, datasheets and our own measurements. For a specific cable, the table on its product page is authoritative.